The present invention generally relates to a redundant clock combiner device and, in particular, relates to such a device that recovers a clock signal from either of two clocks after loss of both.
In many modern systems utilizing digital devices, the system is synchronized by a clock signal that is usually external to the system. The external clock signal, in one form or another, is provided to each device within the system requiring a clock signal, thus ensuring an internal clock mechanism for synchronous operation. In such a system, synchronous operation, among a plurality of digital devices, occurs unless, or until, the external clock signal is lost or the external clock source malfunctions. Such a loss or malfunction results in a temporary catastrophic failure of the desired synchronous operation of the system. For this reason, many such systems are provided with two clock signals from two different external clock sources, i.e. a redundant clock signal is provided. In order to make use of such a redundant clock signal, a redundant clock combiner or selector is provided to receive both of the externally supplied clock signals and select one of the clock signals for synchronizing the devices within the system.
In general, redundant clock combiner devices are usually based on either phased lock loop designs or on logic fall back designs. In the phased lock loop designs, the output clock to the system is phase locked to one of the externally supplied clock signals. If, for any reason, that externally supplied clock signal disappears, the output is slowly phase locked over to the other externally supplied clock signal. The phase lock loop designs are somewhat difficult to implement due to the analog circuitry.
In conventional logic fall back designs the incoming clock signals are initially compared to each other and if both are present, a preassigned one of the two is given priority. Usually, if the prioritized clock signal is lost, then the redundant clock combiner device digitally switches to the other clock signal. If the first, or prioritized, signal is restored and the second lost, then the redundant clock combiner device switches back to the prioritized signal. Difficulties arise, however, if both signals are lost. In such a situation, the conventional redundant clock combiner devices await the restoration of the prioritized signal and do not recover the clock signal if only the second, or non-prioritized, signal is restored.
Although the actual failure of an external clock would not normally occur frequently, clocks are frequently lost to a system when the system is being upgraded or repaired. Further, under such circumstances, it is not unusual for errors to be made in resuming the operation by restoring the wrong clock signal to the wrong port or in the wrong sequence. For example, the two clock signals may be simultaneously disconnected and the non-prioritized clock reconnected to the system before the prioritized signal that, for one reason or another, may need further work. Under such circumstances, a system using a conventional digital fall back clock combiner fails to recover the clock signal and does not resume synchronous operation until the prioritized signal is restored.